Instruction Scheduling for Hiding Reconfiguration Latency

Reconfigurable computing (RC) is becoming increasingly popular as it bears the promise of combining the flexibility of software with the performance of hardware. Although the huge reconfiguration latency of the available FPGA platforms is a well-known shortcoming of the current Field-programmable Custom Computing Machines (FCCMs), little research in instruction scheduling has been undertaken to eliminate or diminish its negative influence on performance. In this paper, we address such a hardware configuration instruction scheduling when a predefined FPGA area allocation is imposed for the operations executed on the reconfigurable fabric. The algorithm is based on advanced data-flow analyses to anticipate the hardware configurations as soon as possible. The result of the proposed scheduling algorithms are promising as the loopinvariant SET instructions can be moved outside the loop body and redundant hardware configuration instructions (when the FPGA is already configured for the target operation) may be eliminated. In consequence, for real applications when the code efficiency prevails over the compilation time, the proposed scheduling offers an appropriate solution for hiding the huge reconfiguration latency of the current FPGAs. More powerfull compiler techniques are required in order to prevent the current scheduling algorithm from introducing SET instructions inside loops. Keywords— Reconfigurable architecture, compiler, instruction scheduling, reconfiguration latency